In processing integrated circuits, electrical contact must be made among circuit nodes, such as isolated device active regions formed within a single-crystal silicon substrate. These circuit nodes are connected by highly conductive interconnect paths or lines, fabricated above a dielectric or insulating layer which covers the substrate surface. Conductive lines and interconnects ideally have low overall resistance, which resistance depends upon both sheet resistivity and contact resistivity. Traditionally, interconnect lines designed to carry high current electrical signals have been fabricated from metals which provide extremely low sheet resistivity, such as aluminum (.apprxeq.2.6 .mu..OMEGA.-cm), and so the process steps in fabricating the lines are referred to as metallization steps. Alternative materials are often acceptable, however, for local interconnect of nearby circuit elements, for interlayer connection, or for lines carrying low currents.
Interlayer electrical connection must be provided through the insulating layers which separate metallization levels from underlying circuit elements (e.g., active areas, transistor gates), or one metallization level from another. Openings, typically referred to as contact openings or simply "contacts," are etched through the insulating layers and lined or filled with conductive material to provide this interlayer connection. Most efficiently, contacts should be filled simultaneously with the deposition of material forming a conductive interconnect line, thus allowing creation of an interconnect level and the interlevel contact in a single process step.
Unfortunately, such efficient fabrication has become more difficult to achieve as integrated circuits have become more densely packed. Where the insulating layer covering the substrate is thick and planarized, as opposed to thin and conformal over the substrate and gate material, the contact is often referred to as a contact via. The insulating layers must be grown or deposited to a minimum thickness. Too thin an insulating layer results in an intolerably high interlevel capacitances which ties up otherwise available conduction carriers. Thus, as circuit dimensions continue to be scaled down to the submicron level, the contact diameter shrinks in size but the depth of the via, determined by the thickness of the insulating layer, must remain the same. In other words, the aspect ratio of contact vias increases as circuitry becomes more densely packed.
While aluminum and other low-resistance metals (e.g. copper, gold) may have very low sheet resistance, they can be problematic due to contamination of the substrate, which causes parasitic leakage currents or device failure. Diffusion barriers must therefore be formed prior to depositing a metal via fill.
Additionally, metals tend to form poor contact in high aspect ratio vias. Physical deposition of metals, such as by sputtering or evaporation, produces poor step coverage into narrow, deep vias. During a metal sputter deposition, for example, metal builds quickly on the lip of the via, bulging into the via mouth. This results in a shadow effect, sheltering the lower corner of the via from further deposition and leaving only thin metal coverage of the via bottom surface. This thin layer is subject, during circuit operation, to high resistance and electromigration. Electromigration describes the motion of metal ions in response to high density current flow, which may even further thin the metal at the via bottom by piling up the metal in some regions while forming voids elsewhere.
One method of improving step coverage involves a process of sloping the sidewall of the via, thus opening the via in a tapered or cone shape. The minimum diameter of the via bottom, however, is still limited by photolithographic resolution. Sloping the via sidewall thus increases the total area occupied by the via and reduces the allowable packing density. Such decreases in packing density are unacceptable in the face of commercial requirements for the miniaturization of integrated circuits and especially DRAMs.
Chemical vapor deposition (CVD), on the other hand, may yield adequate step coverage, even for the high aspect ratio, vertical vias of current and future DRAMs. CVD polycrystalline silicon (polysilicon or poly), for example, is well known to produce conformal layers in contact vias, or polysilicon plugs which completely fill the via. One drawback to polysilicon plugs is a relatively high sheet resistivity. Additionally, polysilicon can form rectifying contacts with the active areas in these prior art interconnects. The polysilicon layer must therefore be doped to match the dopant type of the contacted active region, in order to ensure ohmic (low resistance) contact. This doping step requires at least one additional mask step, possibly two additional masks where contacted active areas include both n-doped and p-doped regions.
In place of polysilicon plugs, CVD deposition of tungsten (W) has recently seen widespread use in integrated circuit fabrication. FIG. 1 illustrates a typical configuration for a tungsten plug 10 through a contact via 12 which has been etched through an insulating layer 14. The illustrated plug 10 is meant to form contact between an active area 16 and a metal interconnect 18.
Although CVD of tungsten has been developed with good step coverage into vias, multiple processing steps are required for its integration. For example, after the via 12 has been formed, a layer of titanium (Ti) 19 is often laid first. This layer is sintered in a high temperature step at some point in the fabrication process to form a layer of titanium silicide 20 (predominantly TiSi.sub.2) at the Ti/Si interface over the active area 16. The silicide serves to provide good ohmic contact between the plug and the silicon active area 16.
An adhesion layer is also required for efficient deposition into the via 12, due to poor adhesion of CVD tungsten to insulating materials in which the via 12 is formed. A titanium nitride film 22 (TiN) serves this purpose for the illustrated prior art tungsten plug. On the other hand, poor adhesion may remain in other areas, such as the wafer backside, so that an unwanted tungsten film may still delaminate and contaminate the chamber, even with the adhesion layer in the via 12 and over the insulating layer 14.
Furthermore, tungsten demonstrates higher sheet resistivity than aluminum or other conventional metal interconnects, though it is more conductive than polysilicon. Thus, the tungsten plug 10 must be used in conjunction with a lower resistance metal line, such as an aluminum interconnect 18 as illustrated in FIG. 1. Separate chambers are required for the metal interconnect deposition, and for the tungsten plug CVD after via formation. The aluminum should ideally be deposited over a planar surface prior to patterning for interconnect, and aluminum layers over tungsten tend to peel off due to high stress. Thus, the tungsten should remain only in the via, rather than over the entire wafer. If the CVD tungsten is blanket-deposited, a planarizing etchback of the tungsten is necessary to remove the excess tungsten over the insulating layer prior to aluminum deposition, for example. The etchback is difficult because it requires both a sacrificial layer and an etch process with a 1:1 etch rate ratio for the sacrificial layer and the tungsten. Seeding and selective deposit also requires an etchback step if vias of different depths are to be filled simultaneously. Even after the etchback, a second titanium layer 24 is often employed to provide both good electrical contact and good adhesion between the tungsten plug 10 and the aluminum interconnect 18.
These requirements make tungsten plugs expensive and difficult to reliably construct. Additional problems with the formation of tungsten plugs are discussed in "Silicon Processing For the VLSI Era; Vol. 2--Process Integration," by S. Wolf, published 1990 by Lattice Press, Sunset Beach, Calif., at pp. 245-52, which discussion is hereby incorporated by reference.
A need thus exists for a lower cost method of forming conductive plugs in contact vias. Ideally, the method should be capable of forming an interconnect simultaneously with the interlevel contact within the via.